Computing Execution Times with eXecution Decision Diagrams in the Presence of Out-Of-Order Resources
نویسندگان
چکیده
We propose a precise and efficient pipeline analysis to tackle the problem of out-of-order resources in modern embedded microprocessors for computation Worst-Case Execution Time (WCET). Such are prone timing anomalies 1. To remain sound, must either rely on huge over-estimations or consider all possible states which usually leads combinatorial blowup. cope with this situation, we build an computational model by leveraging algebraic properties eXecution Decision Diagram 2 is able track precisely along execution paths analysed program while keeping time within acceptable range. show how apply at Control Flow Graph (CFG) level, account typical resource: shared memory bus between instruction data caches. observe gain precision WCET ranging from 20% 80% compared state-of-the-art OTAWA toolset. The shows that our approach scales realistic benchmarks, making it appropriate industrial applications.
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2023
ISSN: ['1937-4151', '0278-0070']
DOI: https://doi.org/10.1109/tcad.2023.3258752